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wire 2026-10-22
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verl standardizes low-precision rollout kernels on DeepGEMM

By RepoJournal · Filed · About Alignment & Post-training · Composed from the cited sources · methodology

verl's vLLM rollout path now routes FP8, MXFP8 and MXFP4 Linear/MoE kernels through DeepGEMM, aligning it with the SGLang backend policy, while MXFP8/MXFP4/NVFP4 weight refit lands on the SGLang side.

[3/3][vllm] feat: standardize low-precision kernels on DeepGEMM verl-project/verl

by wuxibin89

The vLLM backend now routes supported FP8, MXFP8 and MXFP4 Linear and MoE rollout kernels through DeepGEMM, matching the SGLang policy so training and inference share kernels and stop diverging on activation quantization, scale layouts and fused-MoE epilogues. If you run mixed-precision rollouts, expect kernel selection to resolve differently than before.

[2/3][sglang] feat: support mxfp8/mxfp4/nvfp4 weight refit verl-project/verl

by wuxibin89

SGLang rollout now supports online weight refit for MXFP8, routed-expert MXFP4 and routed-expert NVFP4: the trainer exports pre-quantized checkpoint tensors and a bucket-aware custom loader rebuilds backend-specific layouts after the final sync bucket without replacing CUDA-graph-captured storage. Operators running quantized GRPO-style loops can refit weights in place instead of reloading.

[megatron, trainer] fix: recipe-agnostic THD padding and FP8 padding of top-k distillation tensors (#8325) verl-project/verl

by jimmiezhang

The Megatron trainer's THD padding path is now recipe-agnostic: preprocess_packed_seqs and preprocess_thd_engine take a single integer, quant_align_size, instead of the FP8-specific use_fp8_padding and fp8_recipe arguments, and top-k distillation tensors get the same padding treatment. Callers passing the old FP8 arguments need to migrate to the new signature.

[ci, hardware] fix: fix Ascend multinode GLM5.2 top-16-expert training CI (#8066) verl-project/verl

by lxb007981

The Ascend multinode GLM5.2 top-16-expert CI now unsets HCCL_OP_EXPANSION_MODE in the driver and Ray workers, disables inter-node HCCS in favor of RoCE, and raises worker memory requests and limits to 1536 GiB. Relevant if you mirror that recipe on Ascend clusters.

Link the TPU skill from the TPU SFT guide (#2036) allenai/open-instruct

by Abhishek Rao

Elsewhere, open-instruct linked its TPU skill from the TPU SFT guide, and verl pointed the e2e_ascend workflow's Hugging Face dataset and Megatron config-lock caches at /root/.cache/temp.

Quick answers

What shipped in Alignment & Post-training on October 22, 2026?
verl's vLLM rollout path now routes FP8, MXFP8 and MXFP4 Linear/MoE kernels through DeepGEMM, aligning it with the SGLang backend policy, while MXFP8/MXFP4/NVFP4 weight refit lands on the SGLang side. In total, 10 commits and 10 pull requests landed.
Who contributed to Alignment & Post-training on October 22, 2026?
4 developers shipped this update, including lxb007981, jimmiezhang, wuxibin89, and Abhishek Rao.
What were the notable Alignment & Post-training updates?
[3/3][vllm] feat: standardize low-precision kernels on DeepGEMM, [2/3][sglang] feat: support mxfp8/mxfp4/nvfp4 weight refit, and [megatron, trainer] fix: recipe-agnostic THD padding and FP8 padding of top-k distillation tensors (#8325).