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Open-Instruct moves to Miles v0.1.2; verl fixes teacher top-k packing under CP
By RepoJournal · Filed · About Alignment & Post-training · Composed from the cited sources · methodology
The only two changes an operator can act on today are open-instruct's runtime move to Miles v0.1.2 and a verl fix for teacher logits that matched the student's shape but not its tokens; the rest is CI and device-abstraction plumbing.
Update Miles integration and runtime to v0.1.2 allenai/open-instruct
The runtime now targets Miles v0.1.2: the driver adapts to the new training/publication and manager interfaces, Ray initializes before W&B, and tracking is set up before worker arguments are serialized. The Dockerfile moves in step with FlashInfer Python/cubin 0.6.18, sglang-kernel 0.4.7, and the exact upstream router wheel, so if you run the Open-Instruct training image, this is the version to...
[megatron, trainer] fix: pack the teacher's top-k tensors with the student's CP split verl-project/verl
compute_forward_kl_topk now packs the teacher's top-k tensors with the student's CP split, not just its low-precision padding. Before, on THD the teacher rows could match student_logits in shape and still belong to other tokens; if you run distillation with Megatron and context parallelism, the KL you were computing may not have been the KL you intended.
[hardware, tests] fix: convert hardcoded cuda/nccl from unit tests and linear cross-entropy kernel host code verl-project/verl
The Triton linear cross-entropy host code and unit tests now route through verl.utils.device helpers (get_device_name, get_torch_device, get_device_id, get_nccl_backend, is_device_available) instead of hardcoded "cuda" and "nccl". CUDA behavior is unchanged; the point is Intel XPU support under the verl.plugin.platform accelerator abstraction, so treat this as groundwork rather than a migration...
TPU guide and skill: current slice layout, context-parallel load-balance trap allenai/open-instruct
The TPU guide and skill now describe the current cluster (seven 4x4x8s and three 8x8x16s since 2026-10-21, 128 chips held for auto-repair) and drop the old fallback to the 8x8x8, whose results are marked historical. It also documents a new context-parallel load-balance trap under ici_context_parallel, which is worth reading before you size a TPU job.
[ci] fix: set SP_SIZE=1 temporarily due to the code refactoring of fsdp-turbo backend (#8344) verl-project/verl
Also in verl: SP_SIZE is temporarily pinned to 1 in CI while the fsdp-turbo backend is refactored, the Ascend E2E runs now stop Ray and kill leftover vLLM processes after both GSM8K and GEO3K including on failure, and those workflows relocate HF_DATASETS_CACHE and Megatron config locks off read-only mounts.
Action items
- → Rebuild open-instruct against Miles v0.1.2 with FlashInfer 0.6.18 and sglang-kernel 0.4.7 allenai/open-instruct [plan]
